Programmable logic devices (PLDs) may be used to implement large systems that include millions of gates and megabits of embedded memory. The complexity of large systems often require the use of electronic design automation (EDA) tools to manage and optimize their design and placement onto physical target devices. Of the tasks required in managing and optimizing design and placement, satisfying timing constraints of a system is often the most important and the most challenging. In order to satisfy timing constraints, many iterations are often required to determine how components in logic blocks are to be grouped and where these logic blocks are placed on the target device.
Automated placement algorithms in EDA tools perform the time-consuming task of manually mapping logic blocks to physical locations on their target device. However, even state of the art automated algorithms are sometimes incapable of producing solutions that are comparable to user defined manual placement. User defined manual placement techniques are often able to identify critical sections of logic that should be grouped together in order to meet timing constraints that automated algorithms are slow to or even sometimes unable to identify. In addition, many of the state of the art EDA tools utilize a design process that involves the design of modules that make up logic blocks and the integration of the modules into a system before optimizing the system. Systems using this design process may fail to meet performance requirements despite having individual modules that meet the performance requirements before integration. Furthermore, changes made to one module may affect the performance of other modules. Re-optimizing modules to meet system performance requirements often requires additional design iterations which is undesirable.
Thus, what is needed is an improved method and apparatus for design and placement of components on PLDs. This improved method and apparatus should utilize the positive attributes of manual user placement and automated placement of components on PLDs.